This paper describes a CMOS analogy voltage supper buffer designed to haveextremely low static current Consumption as well as high current drivecapability. A new technique is used to reduce the leakage power of class-ABCMOS buffer circuits without affecting dynamic power dissipation. The name ofapplied technique is TRANSISTOR GATING TECHNIQUE, which gives the high speedbuffer with the reduced low power dissipation (1.105%), low leakage and reducedarea (3.08%) also. The proposed buffer is simulated at 45nm CMOS technology andthe circuit is operated at 3.3V supply[11]. Consumption is comparable to theswitching component. Reports indicate that 40% or even higher percentage of thetotal power consumption is due to the leakage of transistors. This percentagewill increase with technology scaling unless effective techniques areintroduced to bring leakage under control. This article focuses on circuitoptimization and Design automation techniques to accomplish this goal [9].
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